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10-bit, 65/80/105 msps dual a/d converter preliminary technical data ad9216 rev. prd_6 / 15 / 2004 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 7 81.326.8703 ? 2004 analog devices, inc. all rights reserved. features integrated dual 10 - bit a - to - d converters single 3 v supply operation (2.7 v to 3.3 v) snr = 58 dbc (to nyquist, ad9216 - 105) sfdr = 75 dbc (to nyquist, ad9216 - 105) low power: 280mw at 105msps differential input with 500 mhz 3 db bandwidth exception al cross talk immunity > 75db flexible analog input: 1 v p - p to 2 v p - p range offset binary or twos complement data format clock duty cycle stabilizer applications ultrasound equipment if sampling in communications receivers: 3g, radio point - to - point, lmds , mmds battery - powered instruments hand - held scopemeters low cost digital oscilloscopes general description the ad9216 is a dual, 3 v, 10 - bit, 65/80/105 msps analog - to - digital converter. it features dual high performance sample - and hold amplifiers and an i ntegrated voltage reference. the ad9216 uses a multistage differential pipelined architecture with output error correction logic to provide 10 - bit accuracy and guarantee no missing codes over the full operating temperature range at up to 1 05 msps data rate s. the wide bandwidth, differential sha allows for a variety of user selectable input ranges and offsets including single - ended applications. it is suitable for various applications including multiplexed systems that switch full - scale voltage levels in su ccessive channels and for sampling inputs at frequencies well beyond the nyquist rate. dual single - ended clock inputs are used to control all internal conversion cycles. a duty cycle stabilizer is available on the ad9216 (all speed grades) and can compen sate for wide variations in the clock duty cycle, allowing the converters to maintain excellent performance. the digital output data is presented in either straight binary or twos complement format. out - of - range signals indicate an overflow condition, whic h can be used with the most significant bit to determine low or high overflow. fabricated on an advanced cmos process, the ad9216 is available in a space saving 64 - lead lfcsp (9x9) and is specified over the industrial temperature range ( ? 40 c to +85 c). adc d9 a -d 0a output mux/ buffers agnd vin- _a clk_a ad9216 sha 10 vin+_a dcs sense reft_a 10 avdd adc vin-_b sha vin+_b 10 d10 b -d 0b 10 mux_select clk_b agnd drgnd shared_ref pwdn_a dfs mode control + - refb_a reft_b refb_b clock duty cycle stabilizer pwdn_b otr_b oeb_b oeb_a otr_a output mux/ buffers 0.5v vref drvdd figure 1 . functional block diagram product highlights 1. pin compatible with ad9238, dual 12 - bit 20/40/65msps adc and ad9248, dual 14 - bit 20/40/65msps adc. 2. speed grade options off 105 msps, 80 msps, and 65 msps allow flexibility between power, cost, and performance to suit an application. 3. low power consumption: ad9216 - 105: 105 msps = 280 mw ad9216 - 80: 80 msps = 238 mw ad9216 - 65: 65 msps = 215mw 4. the patented sha input maintains excellent performance for input frequencies up to 100 mhz and can be configured for single - ended or differential operation. 5. typical channel isolation of 75 db @ f in = 10 mhz. 6. the clock duty cycle stabilizer maintains performance over a wide range of clock duty cycles.
ad9216 preliminary technical data rev. prd page 2 of 20 6/15/2004 table of contents general description ................................ .............................. 1 product highlights ................................ ................................ 1 dc specifications (continued) ................................ ............. 4 switching specifications ................................ ....................... 4 ac specifications ................................ ................................ . 5 absolute maximum ratings ................................ ..................... 7 esd caution ................................ ................................ ......... 7 terminology ................................ ................................ ........ 10 typi cal performance characteristic plots (tbd) .............. 12 equivalent circuits ................................ ................................ . 13 theory of operation ................................ ............................ 13 analog input ................................ ................................ ....... 13 c lock i nput and c onsiderations ................................ .......... 15 power dissipation and standby mode ................................ 15 digital outputs ................................ ................................ .... 15 t iming ................................ ................................ ................ 16 d ata f ormat ................................ ................................ ........ 16 v oltage r eference ................................ ............................... 17 evaluation board diagrams (tbd) ................................ ........ 19 outline dimensions ................................ ................................ 20 revisi on history pra: initial version prb: included specification tables, ordering guide, package and pin configuration and theory of operation sections. prc: corrected pin configuration figure (fig3) pin naming errors , updated supply spec, corrected timing diagram and latency. prd: removed 120msps grade, updated dcs,oeb_b pin descriptions, updated input referred noise, demux timing diagram needs updating
preliminary technical data ad9216 rev. prd page 3 of 20 6/15/2004 ad9216especifications dc specifications table 1 . (avdd = 3 v, drvdd = 2.5 v, maximum sample ra te, clk_a = clk_b; ain = -0.5 dbfs differential input, 1.0 v internal reference, tmin to tmax, unless otherwise noted.) test ad9216bcp - 65/80 ad9216bcp - 105 parameter temp level min typ max min typ max unit resolution full vi 10 10 bits accuracy no missing codes guaranteed full vi 10 10 bits offset error full vi 0.3 tbd 0.30 tbd % fsr gain error 1 full iv 1.0 tbd 1.0 tbd % fsr differential nonlinearity (dnl) 2 full v 0.5 0.5 lsb 25c i 0.5 tbd 0.5 tbd lsb in tegral nonlinearity (inl) 2 full v 0.5 0.5 lsb 25c i 0.5 tbd 0.5 tbd lsb temperature drift offset error full v 15 15 ppm/c gain error 1 full v 30 30 ppm/c internal voltage reference output voltage error (1 v mode) full vi 5 35 5 35 mv load regulation @ 1.0 ma full v 0.8 0.8 mv output voltage error (0.5 v mode) full v 2.5 2.5 mv load regulation @ 0.5 m a full v 0.1 0.1 mv input referred noise input span = 1 v 25c v 0.8 0.8 lsb rms input span = 2.0 v 25c v 0.4 0.4 lsb rms analog input input span = 1.0 v full iv 1 1 v p - p input span = 2.0 v full iv 2 2 v p - p input capacitance 3 full v 2 2 pf reference input resistance full v 7 7 k ? power supplies supply voltages avdd full iv 2.7 3.0 3.3 2.7 3.0 3.3 v drvdd full iv 2.25 2.5 3.6 2.25 2.5 3.6 v supply current iavdd 2 full v tbd/tbd tbd ma idrvdd 2 full v tbd/tbd tbd ma psrr full v 0.01 0.01 % fsr power consumption dc input 4 full v tbd/tbd tbd mw sine wave input 2 full vi 215/238 280 mw standby power 5 full v 1/1 1 mw matching characteristics offset error full v 0.1 0.1 % fsr gain error full v 0.05 0.05 % fsr 1 gain error and gain temperature coefficient are based on the a/d converter only (with a fixed 1.0 v external reference). 2 measured at maximum clock rate with a low frequency sine wave inpu t and approximately 5 pf loading on each output bit. 3 input capacitance refers to the effective capacitance between one differential input pin and avss. refer to figure xx for the equivalent analog input structure. 4 measured wit h dc input at maximum clock rate. 5 standby power is measured with the clk_a and clk_b pins inactive (i.e., set to avdd or agnd). specifications subject to change without notice.
ad9216 preliminary technical data rev. prd page 4 of 20 6/15/2004 dc specifications (c o ntinued) table 2 . (avdd = 3 v, drvdd = 2.5 v, maximum sample rate, clk_a = clk_b; ain = -0.5 dbfs differential input, 1.0 v internal reference, tmin to tmax, unless otherwise noted.) test ad9216bcp - 65/80 ad9216bcp - 105 unit parame ter temp level min typ max min typ max logic inputs high level input voltage full iv 2.0 2.0 v low level input voltage full iv 0.8 0.8 v high level input current full iv - 10 +10 - 10 +10 a low level input current full iv - 10 +10 - 10 +10 a input capacitance full iv 2 2 pf logic outputs 1 drvdd = 2.5v high level output voltage full iv 2.45 2.45 v low level output voltage full iv 0.05 0.05 v 1 output voltage levels measured with 5 pf load on each output. specifications subject to change without notice. switch ing specifications table 3 . switching specifications test ad9216bcp - 65/80 ad9216bcp - 105 parameter temp level min typ max min typ max unit switching performance max conversion rate full vi 65/80 105 msps min conve rsion rate full v 1 1 msps clk period full v 15.4/12.2 9.5 ns clk pulsewidth high 1 full v 6.2/5 4.2 ns clk pulsewidth low 1 full v 6.2/5 4.2 ns data output parameter output delay 2 (t pd ) full vi 2.0 4.8 6.0 2.0 4.8 6.0 ns pipel ine delay (latency) full v 6 6 cycles aperture delay (t a ) full v 1.0 1.0 ns aperture uncertainty (t j ) full v 0.5 0.5 ps rms wake - up time 3 full v 2.5 2.5 ms out - of - range recovery time full v 2 2 1 the ad9216 has a duty cycle stab ilizer circuit that, when enabled, corrects for a wide range of duty cycles (see tpc xx). 2 output delay is measured from clock 50% transition to data 50% transition, with a 5 pf load on each output. 3 wake - up time is dependent on the value of the decoupli ng capacitors; typical values shown with 0.1 f and 10 f capacitors on reft and refb. specifications subject to change without notice. t a t pd n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n-1 n n+1 analog input clk data out n ? 1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 figure 2 . timing diagram
preliminary technical data ad9216 rev. prd page 5 of 20 6/15/2004 ac specifications table 4 . (avdd = 3 v, d rvdd = 2.5 v, maximum sample rate, clk_a = clk_b; ain = ? 0.5 dbfs differential input, 1.0 v internal reference, tmin to tmax, unless otherwise noted.) test ad9216bcp - 65/80 ad9216bcp - 105 parameter temp level min typ max min typ max unit signal - to - noise ratio f input = 2.4 mhz 25c v 58 57 dbc f input = 19.6 mhz full v 58 dbc 25c iv tbd 58 dbc f input = 32.5 mhz full v 57 dbc 25c iv tbd 57 dbc f input = 69 mhz full v dbc 25c iv dbc f input = 100 mhz 25 c v 57 56 dbc signal - to - noise and distortion ratio f input = 2.4 mhz 25c v 58 57 dbc f input = 19.6 mhz full v 58 dbc 25c iv tbd 58 dbc f input = 32.5 mhz full v 57 dbc 25c iv tbd 56 dbc f input = 69 mhz full v dbc 25c iv dbc f input = 100 mhz 25c v 56 55 dbc effective number of bits (enob) f input = 2.4 mhz 25c v 9.4 9.3 bits f input = 19.6 mhz full v 9.4 bits 25c i tbd 9.4 bits f input = 32.5 mhz full v 9.3 bit s 25c i tbd 9.1 bits f input = 69 mhz full v bits 25c i bits f input = 100 mhz 25c v 9.1 8.9 bits total harmonic distortion f input = 2.4 mhz 25c v - 70.0 - 70.0 dbc f input = 19.6 mhz full v - 69.0 dbc 25c i - 70.0 tbd dbc f input = 32.5 mhz full v - 69.0 dbc 25c i - 68.0 tbd dbc f input = 69 mhz full v dbc 25c i dbc f input = 100 mhz 25c v - 67.0 - 66.0 dbc worst harmonic (2nd or 3rd) f input = 19.6 mhz full v - 75.0 dbc f input = 32.5 mhz full v - 74.0 dbc f input = 69 mhz full v dbc spurious free dynamic range f input = 2.4 mhz 25c v 75.0 75.0 dbc f input = 19.6 mhz full v 75.0 dbc 25c i tbd 75.0 dbc f input = 32.5 mhz full v 74.0 dbc 25c i tbd 74.0 dbc f input = 69 mhz full v dbc 25c i dbc
ad9216 preliminary technical data rev. prd page 6 of 20 6/15/2004 f input = 100 mhz 25c v dbc crosstalk full v - 80.0 - 80.0 db specifications subject to change without notice.
preliminary technical data ad9216 rev. prd page 7 of 20 6/15/2004 absolute maximum ratings table 5 . ad9216 absolute maximum ratings 1 parameter rating pin name with respect to min max unit electrical avdd agnd - 0.3 +3.9 v drvdd drgnd - 0.3 +3.9 v agnd drgnd - 0.3 +0.3 v avdd drvdd - 3.9 +3.9 v digital outputs clk, dcs, mux_s elect, shared_ref, drgnd - 0.3 drvdd + 0.3 v oeb, dfs agnd - 0.3 avdd + 0.3 v vina, vinb agnd - 0.3 avdd + 0.3 v vref agnd - 0.3 avdd + 0.3 v sense agnd - 0.3 avdd + 0.3 v refb, reft agnd - 0.3 avdd + 0.3 v pdwn agnd - 0.3 avdd + 0.3 v environmental 2 operating temperature - 45 +85 c junction temperature +150 c lead temperature (10 sec) +300 c storage temperature - 65 +150 c 1 absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 typical thermal impedances (64 - lead lqfp); ? ? j a = 54c/w. these measurements were taken on a 4 - layer board in still air, in accordance with eia/jesd51 - 7. explanation of test levels i 100% production tested. ii 100% production tested at 25c and sample tested at specifie d temperatures. iii sample tested only. iv parameter is guaranteed by design and characterization testing. v parameter is a typical value only. vi 100% production tested at 25c; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge witho ut detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation o r loss of functionality.
ad9216 preliminary technical data rev. prd page 8 of 20 6/15/2004 table 6 . ordering guide model temperature range package description package option ad9216bcp - 65 ? 40c to +85c 64 - lead lead frame chip scale package (lfcsp) ad9216bcpz - 80 ? 40c to +85c 64 - lead lea d frame chip scale package (lfcsp) ad9216bcpz - 105 ? 40c to +85c 64 - lead lead frame chip scale package (lfcsp) ad9216bcpzrl7 - 65 ? 40c to +85c 64 - lead lead frame chip scale package (lfcsp) ad9216bcpzrl7 - 80 ? 40c to +85c 64 - lead lead frame chip scale package (lfcsp) ad9216bcpzrl7 - 105 ? 40c to +85c 64 - lead lead frame chip scale package (lfcsp) ad9216 - 65pcb evaluation board with ad9216bcpz - 65 ad9216 - 40pcb evaluation board with ad9216bcpz - 80 ad9216 - 105pcb evaluation board with ad9216bcpz - 105 a d9216 6 4 l e a d f o r l f - c s p t o p v i e w ( n o t t o s ca l e ) 1 1 a g n d v i n - _ a a g n d a v d d r e f t _ a r e f b _ a v r e f s e n s e 1 3 4 5 6 7 1 2 8 9 2 3 1 4 1 0 1 5 1 r e fb_ b r e ft_ b a v d d a g n d v i n+_ b 1 6 v i n-_ b v i n + _ a a g n d d 2 _ a d 0 _ a d n c d n c d n c d n c d r v d d d r g n d o t r _ b d 9 _ b ( m s b ) d 8 _ b d 7 _ b d 6 _ b d 5 _ b 3 8 3 6 4 5 4 4 4 3 4 2 3 7 4 1 4 0 4 7 4 6 3 5 3 9 3 4 4 8 d 1 _ a 3 3 d 4 _ b 2 7 a v d d d c s d f s p d w n _ b o e b _ b d n c d n c d n c d n c 2 9 2 0 2 1 2 2 2 3 2 8 2 4 2 5 1 8 1 9 3 0 2 6 3 1 1 7 d 0 _ b d r v d d d 1 _ b d 2 _ b 3 2 d 3 _ b c l k _ b d r g n d c l k _ a d 9 _ a ( m s b ) 5 4 5 2 6 1 6 0 5 9 5 8 5 3 5 7 5 6 6 3 6 2 5 1 5 5 5 0 6 4 4 9 a v d d s h a r e d _ r e f m u x _ s e l e c t p d w n _ a o e b _ a d 8 _ a d 7 _ a d 6 _ a d r g n d d r v d d d 5 _ a d 4 _ a d 3 _ a o t r _ a figure 3 . pin configuration
preliminary technical data ad9216 rev. prd page 9 of 20 6/15/2004 table 7 . pin function descriptions pin number mnemonic description 2 vin+_a analog input pin (+) for channel a 3 vin ? _a analog input pin ( - ) for channel a 15 vin+_b analog input pin (+) for channel b 14 vin - _b analog input pin ( - ) for channel b 6 reft_a differential reference (+) for channel a 7 refb_a differential reference ( - ) for channel a 11 reft_b differential reference (+) for channel b 10 refb_b di fferential reference ( - ) for channel b 8 vref voltage reference input/output 9 sense reference mode selection 18 clk_b clock input pin for channel b 63 clk_a clock input pin for channel a 19 dcs enable duty cycle stabilizer (dcs) mode ( tie to avdd t o enable) 20 dfs data output format select bit (low for offset binary, high for twos complement) 21 pdwn_b power - down function selection for channel b (active high) 60 pdwn_a power - down function selection for channel a (active high) 22 oeb_b output ena ble bit for channel b (low setting enables channel b output data bus) 59 oeb_a output enable bit for channel a (low setting enables channel a output data bus) 46 ? 51, 54 - 57 d0_a (lsb) - d9_a (msb) channel a data output bits 27, 30 - 38 d0_b (lsb) ? d9_b (msb) channel b data output bits 39 otr_b out - of - range indicator for channel b 58 otr_a out - of - range indicator for channel a 62 shared_ref shared reference control bit (low for independent reference mode, high for shared reference mode) 61 mux_select data m ultiplexed mode. (see description for how to enable; high setting disables output data multiplexed mode) 5, 12, 17, 64 avdd analog power supply 1, 4, 13, 16 agnd analog ground 28, 40, 53 drgnd digital output ground 29, 41, 52 drvdd digital output drive r supply. must be decoupled to drgnd with a minimum 0.1 f capacitor. recommended decoupling is 0.1 f capacitor in parallel with 10 f 23 - 26, 42 - 45 dnc do not connect pins. should be left floating.
ad9216 preliminary technical data rev. prd page 10 of 20 6/15/2004 terminology aperture delay aperture delay is a mea sure of the sample - and - hold amplifier (sha) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. aperture jitter the variation in aperture delay for successive samples, which is manifested as noise on the input to the a/d converter. integral nonlinearity (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential nonlinearity (dnl, no missing codes) an i deal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 10 - bits resolution indicates that all 2048 codes must be present over all operating ranges. offset error the major c arry transition should occur for an analog value 1/2 lsb below vin+ = vin - . offset error is defined as the deviation of the actual transition from that point. gain error the first code transition should occur at an analog value 1/2 lsb above negative full scale. the last transition should occur at an analog value 1 1/2 lsb belo w the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. temperature drift the temperature drift for zero error and gain error s pecifies the maximum change from the initial (25c) value to the value at t min or t max . power supply rejection the specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. total harmonic distortion (thd) the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal, expressed as a percentage or in decibels relative to the peak carrier signal (dbc). signal - to - noise and distortion (s/n+d, sinad) ratio the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/n+d is expressed in decibels rela tive to the peak carrier signal (dbc). effective number of bits (enob) using the following formula: effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured sinad . signal - to - noise ratio (snr) the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels relative to the peak carri er signal (dbc). spurious free dynamic range (sfdr) the difference in db between the rms amplitude of the input signal and the peak spurious signal. nyquist sampling when the frequency components of the analog input are below the nyquist frequency (f clock / 2), this is often referred to as nyquist sampling. if sampling due to the effects of aliasing, an adc is not necessarily limited to nyquist sampling. higher sampled frequencies will be aliased down into the first nyquist zone (dc - f clock /2) on the output of the adc. care must be taken that the bandwidth of the sampled signal does not overlap nyquist zones and alias onto itself. nyquist sampling performance is limited by the bandwidth of the input sha and clock jitter (jitter adds more noise at higher input frequencies). two - tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. out - of - range recovery time out - of - range re covery time is the time it takes for the a/d converter to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. ( ) 02 6 76 1 sinad enob . . - =
preliminary technical data ad9216 rev. prd page 11 of 20 6/15/2004 crosstalk c oupling onto one channel being driven by a ( - 0.5 dbfs) signal when the adjacent interfering channel is driven by a full - scale signal. measurement includes all spurs resulting from both direct coupling and mixing components.
ad9216 preliminary technical data rev. prd page 12 of 20 6/15/2004 typical performance characteristic plots (tbd)
preliminary technical data ad9216 rev. prd page 13 of 20 6/15/2004 equivalent circuits figure xx. equivalent analog input circuit figure xx. equivalent digital output circuit figure xx. equivalent digital input circuit theory of operation the ad9216 consists of two high performance analog - to - digital converters (adcs) that are based on the ad9215 converter core. the dual adc paths are independent, except for a shared internal band gap reference source, vref. each of the adc?s paths consists of a proprietary front end sample - and - hold amplifi er (sha) followed by a pipelined switched capacitor adc. the pipelined adc is divided into three sections, consisting of a 4 - bit first stage followed by five 1.5 - bit stages and a final 3 - bit fl ash. each stage provides sufficient overlap to correct for fl ash errors in the preceding stages. the quantized outputs from each stage are combined through the digital correction logic block into a final 10 - bit result. the pipelined architecture permits the first stage to operate on a new input sample, while the rem aining stages operate on preceding samples. sampling occurs on the rising edge of the respective clock. each stage of the pipeline, excluding the last, consists of a low resolution fl ash adc and a residual multiplier to drive the next stage of the pipeli ne. the residual multiplier uses the fl ash adc output to control a switched capacitor digital - to - analog converter (dac) of the same resolution. the dac output is subtracted from the stage?s input signal and the residual is amplified (multiplied) to drive the next pipeline stage. the residual multiplier stage is also called a multiplying dac (mdac). one bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the in put stage contains a differential sha that can be configured as ac - or dc - coupled in differential or single - ended modes. the output - staging block aligns the data, carries out the error correction, and passes the data to the output buffers. the output buffe rs are powered from a separate supply, allowing adjustment of the output voltage swing. analog input the analog input to the ad9216 is a differential switched capacitor, sha, that has been designed for optimum performance while processing a differential in put signal. the sha input accepts inputs over a wide common - mode range. an input common - mode voltage of mid supply is recommended to maintain optimal performance. the sha input is a differential switched capacitor circuit. in figure 4 , the clock signal alternatively switches the sha between sample mode and hold mode. when the sha is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one - half of a clock cycle. a small re sistor in series with each input can
ad9216 preliminary technical data rev. prd page 14 of 20 6/15/2004 help reduce the peak transient current required from the output stage of the driving source. also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. this passive network will create a low - pass filter at the adc?s input; therefore, the precise values are dependant on the application. in if under sampling applications, any shunt capacitors should be removed. in combination with the driving source impedance, they would limit the i nput bandwidth. for best dynamic performance, the source impedances driving vin+ and vin - should be matched such that common - mode settling errors are symmetrical. these errors will be reduced by the common - mode rejection of the adc. figure 4 . switched capacitor input an internal differential reference buffer create s positive and negative reference voltages, reft and refb, respectively, that define the span of the adc core. the output common - mode of the reference buffer is set to midsupply, and the reft and refb voltages and span are defined as follows: ( ) ref v avdd 2 1 reft + = ( ) ref v avdd refb - = 2 1 ( ) ref v 2 refb reft 2 span = - = it can be seen from the equations above that the reft and refb voltages are symmetrical about the mid - supply voltage and, by definition, the input span is twice the value of the v ref voltage. the i nternal voltage reference can be pin - strapped to fixed values of 0.5 v or 1.0 v, or adjusted within the same range as discussed in the internal reference connection section. maximum snr performance will be achieved with the ad9216 set to the largest input span of 2 v p - p . the relative snr degradation will be 3 db when changing from 2 v p - p mode to 1 v p - p mode. the sha may be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. the minimum and maximum common - mode input levels are defined as follows: 2 v vcm ref min = ( ) 2 v avdd vcm ref max + = the minimum common - mode input level allows the ad9216 to accommodate ground - referenced inputs. although optimum performance is achieved with a differential in put, a single - ended source may be driven into vin+ or vin - . in this configuration, one input will accept the signal, while the opposite input should be set to mid - scale by connecting it to an appropriate reference. for example, a 2 v p - p signal may be applied to vin+ while a 1 v reference is applied to vin - . the ad9216 will then accept an input signal varying between 2 v and 0 v. in the single - ended configuration, distortion performance may degrade significantly as compared to the differential case. however, the effect will be less noticeable at lower input freque ncies and in the lower speed grade models (ad9216 - 65 and ad9216 - 80). differential input configurations as previously detailed, optimum performance will be achieved while driving the ad9216 in a differential input configuration. for base band applications, the ad8138 differential driver provides excellent performance and a flexible interface to the adc. the output common - mode voltage of the ad8138 is easily set to avdd/2, and the driver can be configured in a sallen - key filter topology to provide band limiti ng of the input signal. at input frequencies in the second nyquist zone and above, the performance of most amplifiers will not be adequate to achieve the true performance of the ad9216. this is especially true in if under sampling applications where freque ncies in the 70 mhz to 200 mhz range are being sampled. for these applications, differential transformer coupling is the recommended input configuration, as shown in figure 5 . figure 5 . differential tran sformer coupling the signal characteristics must be considered when selecting a transformer. most rf transformers will saturate at frequencies below a few mhz, and excessive signal power can also cause core saturation, which leads to distortion. single - end ed input configuration a single - ended input may provide adequate performance in ad9216
preliminary technical data ad9216 rev. prd page 15 of 20 6/15/2004 cost - sensitive applications. in this configuration, there will be a degradation in sfdr and in distortion performance due to the large input common - mode swing. however, if the source impedances on each input are matched, there should be little effect on snr performance. c lock i nput and c onsiderations typical high speed adcs use both clock edges to generate a variety of internal timing signals, and as a result may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the ad9216 provides separate clock inputs for each channel. the optimum performance is achieved with the clocks operated at th e same frequency and phase. clocking the channels asynchronously may degrade performance significantly. in some applications, it is desirable to skew the clock timing of adjacent channels. the ad9216?s separate clock inputs allow for clock timing skew (typ ically 1 ns) between the channels without significant performance degradation. the ad9216 contains two clock duty cycle stabilizers, one for each converter, that retime the non - sampling edge, providing an internal clock with a nominal 50% duty cycle. fas ter input clock rates (where it becomes difficult to maintain 50% duty cycles) can benefit from using dcs as a wide range of input clock duty cycles can be accommodated. maintaining a 50% duty cycle clock is particularly important in high speed applicatio ns, when proper track - and - hold times for the converter are required to maintain high performance. the dcs can be enabled by tying the dcs pin high. the duty cycle stabilizer utilizes a delay locked loop to create the non - sampling edge. as a result, any cha nges to the sampling frequency will require approximately 2 s to 3 s to allow the dll to acquire and settle to the new rate. high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given full - scale in put frequency (f input ) due only to aperture jitter (t j ) can be calculated with the following equation: [ ] j t f p 2 1 10 20 radation snr input = log deg in the equation, the rms aperture jitter, t j , represents the root - sum square of all jitter sources, which includes the clock in put, analog input signal, and adc aperture jitter specification. under - sampling applications are particularly sensitive to jitter. for optimal performance, especially in cases where aperture jitter may affect the dynamic range of the ad9216, it is importa nt to minimize input clock jitter. the clock input circuitry should use stable references, for example using analog power and ground planes to generate the valid high and low digital levels for the ad9216 clock input. power supplies for clock drivers shoul d be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter crystal controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, o r other methods), it should be retimed by the original clock at the last step. power dissipation an d standby mode the power dissipated by the ad9216 is proportional to its sampling rates. the digital (drvdd) power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. the digital drive current can be calculated by n f c v i clock load drvdd drvdd = where n is the number of bits changing and c load is the average load on the digital pins that changed. the analog circu itry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. each speed grade dissipates a baseline power at low sample rates that increases with clock frequency. either channel of the ad9216 c an be placed into standby mode independently by asserting the pwdn_a or pdwn_b pins. it is recommended that the input clock(s) and analog input(s) remain static during either independent or total standby, which will result in a typical power consumption of 1 mw for the adc. note that if dcs is enabled, it is mandatory to disable the clock of an independently powered - down channel. otherwise, significant distortion will result on the active channel. if the clock inputs remain active while in total standby mod e, typical power dissipation of tbd mw will result. the minimum standby power is achieved when both channels are placed into full power - down mode (pdwn_a = pdwn_b = hi). under this condition, the internal references are powered down. when either or both of the channel paths are enabled after a power - down, the wake - up time will be directly related to the recharging of the reft and refb decoupling capacitors and to the duration of the power - down. typically, it takes approximately 5 ms to restore full operatio n with fully discharged 0.1 f and 10 f decoupling capacitors on reft and refb. a single channel can be powered down for moderate power savings. the powered - down channel shuts down internal circuits, but both the reference buffers and shared reference re main powered. because the buffer and voltage reference remain powered, the wake - up time is reduced to several clock cycles. digital outputs the ad9216 output drivers can be configured to interface with 2.5 v or 3.3 v logic families by matching drvdd to the digital supply of the interfaced logic. the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. however, large drive currents tend to cause current glitches on the supplies that may affect converter per formance. applications requiring the adc to drive large capacitive loads or large fan - outs may require external buffers or latches.
ad9216 preliminary technical data rev. prd page 16 of 20 6/15/2004 the data format can be selected for either offset binary or twos complement. this is discussed later in the data format sect ion. t iming the ad9216 provides latched data outputs with a pipeline delay of six clock cycles. data outputs are available one propagation delay (t pd ) after the rising edge of the clock signal. refer to figure 2 for a detailed timi ng diagram. the internal duty cycle stabilizer can be enabled on the ad9216 using the dcs pin. this provides a stable 50% duty cycle to internal circuits. the length of the output data lines and loads placed on them should be minimized to reduce transients within the ad9216. these transients can detract from the converter?s dynamic performance. the lowest typical conversion rate of the ad9216 is 1 msps. at clock rates below 1 msps, dynamic performance may degrade. figure 6 . needs updating example of multiplexed data format using the channel a output and the same clock tied to clk_a, clk_b, and mux_select d ata f ormat the ad9216 data output format can be configured for either twos complement or offset bin ary. this is controlled by the data format select pin (dfs). connecting dfs to agnd will produce offset binary output data. conversely, connecting dfs to avdd will format the output data as twos complement. the output data from the dual a/d converters can be multiplexed onto a single 10 - bits output bus. the multiplexing is accomplished by toggling the mux_select bit, which directs channel data to the same or opposite channel data port. when mux_select is logic high, the channel a data is directed to channel a output bus, and channel b data is directed to the channel b output bus. when mux_select is logic low, the channel data is reversed, i.e., channel a data is directed to the channel b output bus and channel b data is directed to the channel a output bus. by toggling the mux_select bit, multiplexed data is available on either of the output data ports. if the adcs are run with synchronized timing, this same clock can be applied to the mux_select bit. after the mux_select rising edge, either data port will ha ve the data for its respective channel; after the falling edge, the alternate channel?s data will be placed on the bus. typically, the other unused bus would be disabled by setting the appropriate oeb high to reduce power consumption and noise. figure 6 shows an example of multiplex mode. when multiplexing data, the data rate is two times the sample rate. note that both channels must remain active in this mode and that each channel's power - down pin must remain low.
preliminary technical data ad9216 rev. prd page 17 of 20 6/15/2004 v oltage r eferenc e a stable and accurate 0.5 v voltage reference is built into the ad9216. the input range can be adjusted by varying the reference voltage applied to the ad9216, using either the internal reference with different external resistor configurations or an exte rnally applied reference voltage. the input span of the adc tracks reference voltage changes linearly. if the adc is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (common mode voltage). the shar ed reference mode allows the user to connect the references from the dual adcs together externally for superior gain and offset matching performance. if the adcs are to function independently, the reference decoupling can be treated independently and can p rovide superior isolation between the dual channels. to enable shared reference mode, the shared_ref pin must be tied high and external differential references must be externally shorted. (reft_a must be externally shorted to reft_b and refb_a must be shor ted to refb_b.) internal reference connection a comparator within the ad9216 detects the potential at the sense pin and configures the reference into four possible states, which are summarized in table 8 . if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 7 ), setting v ref to 1 v. connecting the sense pin to v ref switches the reference amplifier output to the sense pin, completing the loop and provid ing a 0.5 v reference output. if a resistor divider is connected as shown in figure xx , the switch will again be set to the sense pin. this will put the reference amplifier in a non - inverting mode with the v ref output defined as fo llows: ( ) 1 r 2 r 1 5 0 v ref + = . in all reference configurations, reft and refb drive the adc core and establish its input span. the input range of the adc always equals twice the voltage at the reference pin for either an internal or an external reference. figure 7 . internal reference configuration table 8 . reference configuration summary resulting differential selected mode sense voltage resulting v ref (v) span (v p - p ) external reference avdd n/a 2 external reference internal fixed reference v ref 0.5 1.0 programmable reference 0.2 v to v ref 0.5 (1 + r2/r1) 2 v ref (see figure xx ) internal fixed reference agnd to 0.2 v 1.0 2.0 external reference operation the use of a n external reference may be necessary to enhance the gain accuracy of the adc or to improve thermal drift characteristics. when multiple adcs track one another, a single reference (internal or external) may be necessary to reduce gain matching errors to an acceptable level. a high precision external reference may also be selected to provide lower gain and offset temperature drift. figure 10 shows the typical drift characteristics of the internal reference in both 1 v and 0.5 v modes. when the sense pin is t ied to avdd, the internal reference will be disabled, allowing the use of an external reference. an internal reference buffer will load the external reference with an equivalent 7 k w load. the internal buffer will still generate the positive and negative full - scale references, reft and refb, for the adc core. the input span will always be twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 v. if the internal reference of the ad9216 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. figure x depicts how the internal ref erence voltage is affected by loading. ad9216
ad9216 preliminary technical data rev. prd page 18 of 20 6/15/2004 figure xx. programmable reference configuration figure xx. typical v ref drift figure xx. v ref accuracy vs. load ad9216
preliminary technical data ad9216 rev. prd page 19 of 20 6/15/2004 evaluation board diagrams (tbd)
ad9216 preliminary technical data rev. prd page 20 of 20 6/15/2004 outline dimensions figure 8 . 64 - lead lead frame chip scale package (lfcsp)

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